PROCEEDINGS OF THE IEEE, VOL. 92, NO. 2, FEBRUARY 2004

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RAO R. TUMMALA, FELLOW, IEEE AND JOY LASKAR, SENIOR MEMBER, IEEE

Invited Paper

    The system-on-a-package (SOP) concept is considered as the solution of future communication modules, which would need more functionality, better performance, low cost, and more integrity. In this paper we demonstrate how SOP technology can address the integration platform for future communication system, especially gigabit wireless communications. After the introduction of the SOP concept, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the three-dimensional deployment of core elements such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters enables RF-SOP module development. In the last section we demonstrate how advanced radio architectures that include direct conversion, antenna diversity, and collaborative signal processing are enabled using the SOP technology format. Various ceramic and organic material based multilayer packaging technology has been used for building those integrated modules as well as circuit blocks. In the conclusion, the critical issues and challenges for developing advanced communication platforms using SOP approach are discussed.
  

    Keywords—Communication system, integrated module, integrated radio frequency (RF) passives, multilayer packaging, system-on-a-package (SOP).

    Manuscript received May 12, 2002; revised November 12, 2003.
    The authors are with the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0245 USA.
Digital Object Identifier: 10.1109/JPROC.2003.821902

I.  INTRODUCTION
II.  INTEGRATED PASSIVES
    A.  Multilayer Filter
    B.  Integrated Antenna
    C.  Multilayer Balun
III.  INTEGRATED RF-SOP MODULES
    A.  Ku-Band Transmitter Module
    B.  PA Module With LTCC Embedded Filter
    C.  RF-Front-End Module Using MLO Package
    D.  VCO With High-Q Embedded Inductor
IV.  3-D RF MODULE DEVELOPMENT
    A.  5.8-GHz OFDM Module
    B.  2.4-GHz OFDM Module
V.  SUMMARY AND FUTURE DEVELOPMENTS
ACKNOWLEDGMENT
REFERENCES

I.  INTRODUCTION

    The dawn of the 21st century is witnessing a tremendous demand for wireless (untethered) communications services such as paging, analog and digital cellular telephony, and emerging personal communications services (PCS). Current commercial cellular and PCS systems are concentrated at frequency bands around 900 MHz and 1.8 GHz (S-band); future allocations for PCS systems are expected around 2.4 and 5.8 GHz (through C-band). Beyond the arena of mobile communications, there are numerous wireless applications including RF identification (RFID), satellite communications, local multipoint distribution systems (LMDS), and wireless local area networks (WLANs) operating at frequencies extending into the millimeter-wave regime (Ku to Q-band). The move to higher frequencies has been motivated by the need for more and more bandwidth for multimedia applications such as wireless real-time video transmission and iInternet access, and by the increased overcrowding of the lower frequency bands.
    This rapid expansion of untethered communications services, along with the need for low-cost, high-efficiency system implementations, has led to an explosion in the development of IC approaches in the RF/microwave area. Highly integrated components such as frequency converters, low-noise and power amplifiers, and frequency synthesizers are now commonplace, replacing hybrid circuits employing discrete semiconductor devices. These radio frequency integrated circuits (RFICs) and monolithic microwave integrated circuits (MMICs) are generally packaged together with very large scale integration (VLSI) digital signal processing (DSP) and microprocessor () control chips on multilayer printed circuit boards (PCBs). However, the system-on-a-chip (SOC) movement is ambushed by the cost of additional mask layers needed to marry digital logic with memory and analog function on one specific and optimum substrate.
    

Fig. 1. Advanced MCM solution for gigabit wireless module.

Therefore, many believe that the system-on-a-package (SOP) approach for the next-generation wireless solution is a more feasible option than SOC considering the obstacles faced today by SOC developers. Recent development of materials and processes in packaging area makes it possible to bring the concept of SOP into the RF world to meet the stringent needs in wireless communication area. RF-SOP is “to provide a complete packaging solution for RF module by integrating embedded passives components and MMIC at the package level.� SOP goes one step beyond multichip module (MCM) by enhancing overall performances and adding more functionalities. Wireless devices implementing complex functionality require a large amount of circuitry and consequently, require a large conventional package or MCM real estate. Three-dimensional (3-D) integration techniques using multilayer high-density architectures in different technologies with vertical interconnect and embedded component integration are crucial for the design and development of a single package to a MCM. SOP is the art of bringing together at the system level ICs and embedded components following a codesign philosophy [1][2][3][4][5].
    A strong alternative to complete single-chip integration is some advanced form of an MCM solution, such as the one proposed in Fig. 1, which integrates antenna, filters, resonators, baluns and other RF components. These can be integrated in either ceramic, such as low-temperature cofired ceramic (LTCC), or organic, such as multilayer organic (MLO).
    The basic philosophy here is to fabricate devices and circuits in the optimum available technology for their particular function (e.g., digital circuits in submicrometer CMOS, analog components in BiCMOS, RF components in GaAs or InP) and then integrate them into a system or subsystem using MCM technology.

Fig. 2. Photograph and configuration of the fabricated filter.

High-Q passive structures could potentially be embedded directly into the MCM structure. Multibeam antenna beamforming networks have been demonstrated in MCM technology. For the active analog/RF and digital/DSP functions, individual ICs can be interconnected using flip-chip bonding to eliminate bondwires (and their associated parasitic) and allow more compact MCM floor planning. An additional benefit of this approach is that complete system redesign is not necessarily needed to change one part of the subsystem/module; individual functional component dies could be upgraded as long as their interconnection scheme and footprint were kept the same to remain compatible with the MCM layout. This approach is referred to as system on a package, in contrast to “system on a chip.� The incorporation of microelectromechanical systems (MEMS), smart materials, smart antennas, etc., with mixed-signal ICs in such an environment is now increasingly referred to as “mixed-technology� or “heterogeneous� integration.
    In this paper we focus on the following topics which establish how SOP technology establishes the preferred integration platform for future gigabit wireless needs. First, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the 3-D deployment of core elements such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters, enables RF-SOP module development. In the last section we demonstrate how advanced radio architectures which include direct conversion, antenna diversity, and collaborative signal processing are enabled using the SOP technology format.

II.  INTEGRATED PASSIVES

    A.  Multilayer Filter

    An on-package integrated multilayer filter offers a more attractive implementation than on-chip and discrete filters. An RF image-reject filter was implemented with six layers of LTCC in a stripline configuration whose 3-D view is illustrated in Fig. 2 [6]. Layers 6 and 0 are the top and bottom metallization which serve as the top and bottom ground planes. The two shunt inductors and were realized by the U-shaped strips fabricated on layers 4 and 3, which are located two and three layers underneath the top ground plane, respectively. The end of the strips are connected to both grounds through vias. There is no metallization between layer 4 and 6 and, therefore, the top inductor strip on layer 4 is 7.2 mils (2 layers) away from the top ground plane while the bottom strip is 10.8 mils (3 layers) away from the bottom ground plane. The required mutual inductive coupling is achieved by overlapping the and strips which are one layer (3.6 mils) apart. metal–insulator–metal (MIM) capacitors with electrodes on layers 4 and 3 laid out beside the inductor strips were utilized to implement and . The vertical interconnect capacitor (VIC) topology was utilized to implement , which is realized by two series capacitors of capacitance . Each of these capacitors is implemented in VIC topology as a parallel combination of two capacitors with a value of . Such implementation ensures the symmetry of the structure desirable for high-frequency circuits. If were implemented in MIM topology, the entire structure would not have been symmetrical. The bottom plates of and are used as the top plates of the VIC extended to layer 2 through via connections. The dumbbell-shaped trace is inserted on layer 2 between layer 3 and 1 as the bottom plates of the VIC. The extended top plates of the VIC on layer 1 are used as the top MIM electrodes for the shunt capacitor with the bottom ground on layer 0 as the bottom electrode. The filter prototype is given in Fig. 2. Fig. 3 gives the measured insertion loss of 3 dB at 2.4 GHz with 40-dB rejection at 2 GHz.
    
B.  Integrated Antenna

    One of the major issues for developing RF-SOP is integrating an antenna with a module efficiently.

Fig. 3. Measured and simulated magnitude of S21 for filter.

Fig. 4. Configuration of CBPA.

Fabricating an antenna directly on the package has the advantages of reducing feeder loss and size of an entire module. However, for the frequency range from 1 to 6 GHz, which is being used for the most of wireless mobile and data communication, it is difficult to bring an antenna into the transceiver module, since the size of the antenna becomes large. Also, the interference between the antenna and other RF components in highly compact modules is another main issue in this approach [7].

Fig. 5. Measured and simulated return loss of the CBPA designed for 5.8 GHz.

    For the compact module, the cavity-backed patch antenna (CBPA) has been successfully adopted to LTCC packaging. The configuration of the CBPA is shown in Fig. 4. The antenna is designed to be connected with the embedded RF blocks such as filter or duplexer switches. The cavity structure is formed by surrounding multiple via connected to ground plane. The radiator (patch) is made on the top surface and is connected with the embedded filter through a via. The location of via feed is designed to get impedance matching with an embedded filter. CBPA needs a smaller ground plane, since the most of the energy is confined between the edge of the patch and via-wall. Obviously, thicker substrate increases the bandwidth of the antenna but the thickness should be determined moderately by considering the entire module structure.
    Measured return loss of the CBPA designed for 5.8 GHz is shown in Fig. 5. For comparison, a microstrip patch antenna has been developed for the same frequency. The results shows that bandwidth of CBPA is larger than the patch by 20%.
    
C.  Multilayer Balun

    

Fig. 6. Photograph and configuration of the stripline multilayer balun.

Baluns are required in a wide variety of microwave components such as balanced mixers, push–pull amplifiers, multipliers, and phase shifters. The balun has become one of the important RF components to improve performance and reduce cost of the RF module by embedding it inside of the package [8]. The multilayer balun is presented in this section.

Fig. 7. Measured and simulated results of the stripline balun designed for 5.8 GHz.

    Fig. 6 shows the stripline type multilayer Balun designed for LTCC. Two shorted lines are placed next to an open line such that they couple energy from the open line as shown. The open line is a half wavelength long at the operating frequency. Layers 0 and 4 represent the ground planes of the structure. The half wavelength open line is on layer 2. A small portion of this line is on layer 3 to avoid overlapping traces and in order to achieve the spiral space saving configuration described previously. One of the quarter wavelength coupling sections is on layer 1 and the other on layer 3. Each of these lines is shorted to the ground planes (through vias) above and below it, respectively.

Fig. 8. Configuration and picture of compact Ku-band transceiver module.

    Return loss better than and insertion loss of 3.4 dB is measured as shown in Fig. 7.

III.  INTEGRATED RF-SOP MODULES

    A.  Ku-Band Transmitter Module

    The implementation of compact transmitter modules is a key issue for low power and higher data rates for satellite communications in the Ku/Ka-band range [9]. One obstacle for a compact transceiver module is the large and heavy cavity filter that cannot be easily integrated into the module.

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(b)

Fig. 9. Measured gain of the module. (a) Overall system gain. (b) Gain variation at each level.

    A highly integrated LTCC-based transmitter module using GaAs MESFET MMICs for Ku-band satellite communication applications is presented in Fig. 8. The figure shows the 3-D configuration and picture of the module. The upconverter MMIC integrated with a VCO exhibits a measured upconversion gain of 15 dB and an third-order input intercept point (IIP3) of 15 dBm, while the power amplifier (PA) MMIC shows a measured gain of 31 dB and a 1-dB compression output power of 26 dBm at 14 GHz. Both MMICs were integrated on a compact LTCC module where an integrated front-end bandpass filter (BPF) with a measured insertion loss of 1.8 dB at 14.5 GHz was integrated. The BPF for the transmitter module was implemented in a coupled-line filter topology on a multilayer LTCC substrate. The two stripline ground planes are physically connected by vias and the actual input and output of the filter are connected to the RF amplifier and driver amplifier of the transmitter. Three segment-folded edge-coupled stripline filters, where the middle segment was deployed perpendicular to the first and third segments for compactness, have been designed to suppress the LO signal at 13 GHz as well as the harmonics and spurious signals. This is a balanced stripline topology where the coupled-line segments are sandwiched by two ground planes at an equal distance of 17.5 mils (four LTCC tape layers).
    The entire transmitter chain exhibits a total gain of 32 dB and output power of 26 dBm incorporating the wirebond loss from 14 to 15 GHz and image rejection of more than 30 dBc at 12 GHz as shown in Fig. 9(a). Fig. 9(b) shows the overall system level diagram of the entire transmitter chain based on the measurement of each transmitter blocks. The compact module was made possible by embedding the filter and thereby saving more than 40% of real estate compared to the module if it were implemented on a typical alumina substrate.
    
B.  PA Module With LTCC Embedded Filter

    A 2.4-GHz SiGe heterojunction bipolar transistor (HBT) PA module with a harmonic suppression filter implemented in LTCC substrate has been developed [10]. The harmonic suppression filter and output match network have been implemented completely in LTCC without the use of external discrete components.
    The PA is designed in IBM's commercial SiGe HBT process. It consists of three stages: two driver stages and one power stage; interstage, input, and output match networks; and bias circuits for the three stages. It is packaged in an eight-pin small-outline integrated circuit (SOIC) package. Fig. 10 shows a picture of the developed PA. The harmonic suppression filter and output matching networks are designed in Kyocera's ten layers of LTCC process. Fig. 11 shows the designed filter and output match network. The filter consists of a transmission line in parallel with a capacitor.

Fig. 10. SiGe PA chip.

Fig. 11. Output matching section and harmonic suppression filter built in LTCC substrate.

    The output network is designed to give deep suppression of the second and third harmonics. A length RF-shorted stub is used to achieve a short at the second harmonic. The output matching network, which is also implemented in LTCC using transmission lines and tuned in conjunction with the harmonic suppression filter, presents a short at the second harmonic and nearly an open at the third harmonic.

Fig. 12. Measured performance of the PA module.

Fig. 13. Schematic and picture of MLO-based integrated transmitter module.

    The output power and efficiency of the PA module is shown in Fig. 12. It achieves an output power of 27 dBm at 0–dBm input with a power-added efficiency (PAE) of 45% at 2.4 GHz and . The linear gain of the PA is 35 dB.
    
C.  RF-Front-End Module Using MLO Package

    Organic material-based low-cost MCM-L technology is getting more attention even in the RF area due to its low-cost feature, and despite such disadvantages as high dielectric loss and too much process variation [11][12][13]. A C-band transmitter module incorporating an embedded BPF and an up-converter and a PA MMIC is shown in Fig. 13.
    The transmitter MMIC provides an excellent LO and image rejection fabricated in a commercial GaAs MESFET process. A miniaturized integrated square patch resonator BPF with inset feed lines built in MLO technology has been incorporated to realize a compact and highly integrated transmitter module suitable for the low-cost network interface card (NIC), IEEE 802.11a WLAN applications in the 5–6 GHz frequency band.

(a)

(b)

Fig. 14. Measured performance of up-converter chip, (a) Conversion loss, IIP. (b) Output spectrum.

Fig. 15. Measured performance of embedded BPF (solid: S21; dashed: S11).

    The up-converter MMIC consists of a double-balanced diode ring mixer (DBM), a wide tuning range (20%) voltage controlled oscillator (VCO), a LO buffer amplifier, a IF amplifier, and a RF amplifier. The up-converter MMIC integrated with a VCO exhibits a measured up-conversion gain of 14 dB and an IIP3 of 15 dBm as shown in Fig. 14. LO-to-RF isolation is 45 dB and image rejection of 11 dBc without any bandpass filtering. MLO-based BPF has been implemented and the measured data is shown in Fig. 15. The BPF shows an insertion loss of less than 3 dB and a return loss of 27 dB at 5.8 GHz as well as the image rejection of 35 dBc at 3.8 GHz.
    
D.  VCO With High-Q Embedded Inductor

    A C-band oscillator with external high-Q inductors was built in the MLO package. All circuit blocks except the inductors are implemented in MESFET MMIC [14]. The inductors embedded in the package have been designed to obtain a maximum quality factor around the oscillation frequency.

(a)

(b)

Fig. 16. Comparison of the inductors, on-chip, embedded in MLO and wire-bonding inductors. (a) Q factors. (b) Inductances.

Fig. 17. Phase noise measurement result for the oscillator with MLO inductor.

To validate the VCO with an embedded inductor, the same topology of oscillators having the on-chip inductors, and wire-bonding inductors have also been developed and compared. All the inductors have been designed to get the inductance value of 1.5 nH and optimized to get the highest quality factor in C-band. The measured performances of the three inductors are shown in Fig. 16.
    The TriQuint 0.6 GaAs MESFET process is utilized to design and implement the oscillator circuit. To reduce the noise up-conversion, the cross-coupled differential topology with the capacitive coupling feedback was used. Cross-coupled transistors form a positive feedback to provide a negative resistance to cancel the loss in the LC-resonators. The positive feedback is obtained through capacitors that take the role of suppressing the noise up-conversion as well as dc blocking in order to bias cross-coupled transistors.
    The measurement result of the oscillator with MLO inductor is shown in Fig. 17.

Fig. 18. Proposed 3-D integrated RF front-end concept.

On-wafer measurements of the oscillation frequency, output power, and phase noise were performed using an Agilent 8563E spectrum analyzer. The phase noises of the oscillator with the on-chip inductors and the embedded inductor are and at 600-KHz offset frequency, respectively. Using MLO inductors, the phase noise is 5 dBc/Hz better than the oscillator with on-chip inductors and comparable to the oscillator with wire-bond inductors.

IV.  3-D RF MODULE DEVELOPMENT

    A.  5.8-GHz OFDM Module

    The 3-D integration approach is a very attractive option to increase density, performance and meet the specifications of the next generation wireless communication systems. Very compact 3-D integration technology based on various wafer stacking methods and ultrathin packaging technology have been successfully proposed for digital applications such as 3-D memory and smart cards. However, current 3-D RF-module integration is still based on low-density hybrid assembly technologies. The development of wireless data communication systems in C-Band leads to very stringent specifications for both IC and packaging performances. For these portable and low-powered applications, a high level of integration is also required to reduce essential features such as size, weight and interconnection length.
    We also present a very compact 3-D-integration concept suitable for a RF front-end module by means of substrate stacking method using the ball process [15], [16]. Fig. 18 illustrates the proposed module concept. Two stacked LTCC substrates are used and board-to-board vertical transition is insured by balls. Standard alignment equipment is used to stack the board and, thus, provides a compact, high-performance and low-cost assembly process. Tests structures have been designed for the characterization of balls and an accurate ball modeling shows insertion loss less than 0.1 dB and return loss of up to 10 GHz.

(a)

(b)

Fig. 19. Embedded filter. (a) Schematic. (b) Performance.

    Multistepped cavities into the LTCC boards provide spacing for embedded RF active devices and, thus, provide significant volume reduction by minimizing the gap between the boards. Active devices can be flip chipped as well as wire bonded. A cavity also provides integration opportunity for MEMS device such as MEMS Switch. Passive components, off-chip matching networks, the embedded filter, and the antenna are implemented directly into the LTCC boards by using multilayer technology. Standard BGA balls insure interconnection of this high density module with a motherboard such as an FR4 board. The top and the bottom substrates are dedicated respectively to the receiver and transmitter building blocks of the RF front-end module. The receiver board includes antenna, BPF, active switch, low-noise amplifier (LNA), VCO, and down-conversion mixer. The transmitter board includes up-conversion mixer, PA, and off-chip matching networks. Ground planes and vertical via walls are used to address isolation issues between the transmitter and the receiver functional blocks. Arrays of vertical via are added into the transmitter board to achieve better thermal management.

Fig. 20. Cavity-backed patch antenna layout and performance.

    We have developed a high-performance second-order narrow-band BPF with two cascaded coupled-line sections embedded in stripline configuration to improve insertion loss. A schematic view and measured performance are presented in Fig. 19. Coupled lines have been bent to fit into the module shape and via walls are used to connect ground planes and reduce parallel plate modes. Filter performances have been measured separately and exhibit a insertion loss, return loss, and image rejection greater than as shown in Fig. 19(b).
    

Fig. 21. Rx chipset used in the module. (a) LNA. (b) Mixer. (c) VCO.

A via-fed stacked cavity-backed patch antenna has been designed for IEEE 802.11a 5.8-GHz band as shown in Fig. 20. The heights of the lower and upper patches (400 400 mils) are 8 mils and 32 mils, respectively. The 10-dB return-loss bandwidth of the antenna is about 4%, fully covering the required band (5.725-5.825 GHz). Also, this antenna has a desirable gain (near 6 dBi) and very low cross polarization (less than ).
    

Fig. 22. Tx chipset used in the module. (a) Mixer. (b) RF amplifier.

We used the commercial GaAs MESFET process to implement the Rx and Tx chipset. The Rx chipset consists of LNA, a down-converter mixer, and VCO as shown in Fig. 21. The Tx chipset includes a double-balanced diode ring mixer and RF amplifier as shown in Fig. 22
    The LNA gain is about 13 dB; the LNA noise is about 2.2 dB. Fig. 23(a) shows the output spectrum of the transmitter mixer demonstrating image signal rejection of 11 dBc, and LO-to-RF rejection of 40 dB, across the VCO tuning range between 4.5 and 5.5 GHz. It also shows less than 11-dB conversion loss between IF frequency from dc to 1 GHz. The RF amplifier demonstrates a measured gain of 7 dB as shown in Fig. 23(b).
    
B.  2.4-GHz OFDM Module

(a)

(b)

Fig. 23. Tx module performances. (a) Mixer output spectrum. (b) RF amplifier gain.

Fig. 24. Front-end transceiver architecture.

    In recent years, there has been a great deal of interest in realizing low-power, low-cost, compact RF front-end modules for Bluetooth technology in the 2.4-GHz industrial, scientific, and medical (ISM) band. LTCC technology is well suited for compact wireless transceiver module realization and is becoming increasingly popular for WLAN applications. However, it is quite challenging to integrate the antenna with modules for WLAN applications at 2.4 GHz due to their large size and isolation constraints at higher output powers. Commercial implementations of Bluetooth using SOC technology provide output power levels of 0 and 4 dBm, respectively. The SOP approach allows the development of high-quality passive components on ceramic substrates, thereby providing much higher output power levels (20 dBm). The choice of proper radio architecture and sharing of ground plane among LTCC passive components enables compact implementation of the RF front end (Fig. 24) [17]. Most of today's WLAN solutions aim for very low intermediate frequency (VLIF) RF architectures

Fig. 25. Three-dimensional view of developed module: CMOS transceiver MMICs (LNA, PA, mixer) are on the top layer connected by via structures to embedded passives in LTCC. Loop antenna is separated by ground plane.

for better integration of ICs in commonly available semiconductor processes. For an IF frequency at half the channel bandwidth (500 kHz), the image becomes an adjacent channel according to Bluetooth specifications, thus leading to a looser image rejection specification. We present the development of CMOS MMICs and LTCC multiplayer passive components. These building blocks are then integrated in an LTCC substrate, and an antenna is implemented in the same package.
    An exploded 3-D view of the developed module is shown in Fig. 25. The same filter has been used in transmit and receive paths to save space.
    A CMOS technology has been used in conjunction with commercially available LTCC technology for the complete SOP solution. The 0.24- p–substrate twin-well CMOS technology is similar to most commercially available deep-submicrometer CMOS technologies. The sheet resistance of the silicon substrate is approximately 10 /. It is a five-metal-layer process, and the gate is solicited to reduce gate resistance and transistor.

Table 1 Summary of Specifications of Building Blocks; RF Building Block Performances

    Due to the constant envelope nature of the Gaussian-frequency shift keying (GFSK) modulation scheme, the Bluetooth PA does not have strict linearity requirements. The PA uses a compact three-stage cascade topology. The load-impedance design is based on the load-pull measurement on the power transistor. This PA utilizes on-chip input matching. The output matching is realized in LTCC multilayer high-Q passive elements. Measurement results of the PA show an output power of 20 dBm and a power-added efficiency of 20%. The PA is biased at class-AB and exhibits an output 1-dB compression point of 16.8 dBm. It utilizes a 2.4-mm (40 fingers with 60- gate width) device size.
    The LNA has been designed using a cascode topology. Use of a cascode topology helps in separate optimization of input and output networks, better stability, and better high-frequency operation due to minimization of the Miller capacitor effect. It uses n-channel MOS (NMOS) transistors of 250- widths to achieve low-noise performance. Output matching was optimized to achieve high gain and high IIP3 simultaneously. The LNA has a noise figure of 3 dB, gain of 11 dB, and IIP3 of at 2.45 GHz.
    Double-balanced Gilbert cell topology has been chosen for the up/down conversion mixer. Biasing the mixer core FETs near threshold allows reduced local-oscillator (LO) power for driving the FETs like ideal switches. Two such balanced mixers, with their LO in quadrature, generate a polyphase signal that can be used for image rejection. It uses NMOS transistors of 250- widths for achieving the desired gain from the mixer. It provides a gain of 2 dB and a IIP3 of 0 dBm at of LO power. The LO to IF isolation is greater than 40 dB. Fig. 3 shows a picture of the fabricated chipset used in the module.
    A portion of the total development cost of a transceiver module is expended on this front-end filter, which is typically realized by discrete components. Integrating the filter-on-package is an attractive option, especially with the availability of multilevel dielectric systems, such as that offered by the LTCC process. There are two potential advantages: first, miniaturization is possible by the vertical deployment of filter elements, since there are a large number of dielectric layers available; second, integration essentially eliminates the need for a discrete filter and, therefore, reduces the component and assembly cost. The LTCC-integrated preselect two-resonator BPF described in Section II-A has been adapted designed, developed, and characterized.
    The balun has been implemented using a multilayer coupling structure, occupying a total of five dielectric layers (Fig. 5). Two shorted transmission lines (A and B) are placed next to an open-circuited line (C) such that they couple energy from the open circuited line that has a length of half a wavelength at the desired frequency. This being the case, a standing wave will form a short circuit at the center of the open-circuited line. Here, the current will be at its maximum value. At equal distances away from the center and on either side of it, the voltage will be equal in magnitude but in opposite phases. The two short-circuited line sections are coupled from both ends of the open-circuited line. Therefore, a signal incident at port 1 induces signals at port 2 and port 3 with equal amplitudes but opposite phases. The short-circuited lines have to be approximately a quarter-wavelength long in order to achieve the desired characteristics.
    The antenna utilizes a 3-D loop structure with a vertically embedded loop radiator in 20 LTCC layers for compactness and integration in the same package. A microstrip-transmission line is used for the antenna feed. To minimize the interference between the antenna and other components inside the package, a vertical ground wall using a row of vias has been inserted between the radiator and transceiver. The ground plane of the microstrip transmission-line feed is implemented on layer 18 of the LTCC substrate. The antenna has a size of but can be further optimized by meandering the vertical loop radiator. The measured input-return loss of the antenna is shown in Fig. 7 and is 20 dB at 2.3 GHz. It shows a return loss of at 2.3 GHz. This drift from the desired frequency can be caused by a finite dielectric effect that was not considered in this method of moment simulation.
    Table 1 shows the specifications of each of the building blocks in detail. The MMICs are connected to the embedded passive structures by via interconnections.

V.  SUMMARY AND FUTURE DEVELOPMENTS

    We have presented the SOP concept applied for RF front-end module integration. The development of an LTCC-based component for wireless RF-SOP applications has been described. Various types of multilayer embedded passive components including inductor, capacitor, filter, antenna, and balun suitable for the highly integrated module have been presented. Development efforts on a 3-D integrated module, which include a OFDM transceiver, a Ku-Band transmitter, and 1.9-GHz DECT PA modules, have been demonstrated and then a novel 3-D integration concept has been described for 2.4- and 5.8-GHz applications. Multilayer organic packaging developed for SOP is finally reported. A high Q-factor inductor and embedded filter have been presented as an example of the high performances of multilayer organic package.
    The SOC movement is ambushed by the cost of additional mask layers needed to marry digital logic with memory and analog functions on one specific and optimum substrate. Rather than SOCs, the industry will move instead to 3-D systems to meet the changing needs of the market toward the future third-generation mobile phones as an example. The key will be integrate the optimum technologies together in what one can call a SO3-D, a system-in-3-D package. The package becomes up front part of the architecture, and it would require 3-D floor planning and design.
    Furthermore, the spread of high-performances workstations and PCs in offices and factories create emerging needs for very high data rate wireless transmission. The inflexibility of hardwired networks makes wireless indoor communication systems such as WLAN attractive because of their layout flexibility and portability of terminals. For such short-range indoor broadband WLAN systems, the millimeter-wave band at 60 GHz offers significant advantages supplying very wide bandwidth for the multigigabit-per-second transmission of various multimedia content.
    The SOP evolution for gigabit wireless applications involves systems, technology, and materials consideration. We are targeting 3-D high density module technologies for SOP-based solutions for wireless communication applications.
    First, new materials have to be exploited to provide enhanced organic solution. LCP films offer a unique combination of high-performance properties including chemical resistance, barriers properties, temperature resistance, mechanical strength, and stiffness and very good high-frequency properties. This places LCP as an optimum candidate for advanced MCM-L technology without the need of using a core substrate as a mechanical carrier.
    Special care is required in the interconnection technique for IC-to-board and board-to-board transition to maintain ground, 50- matching continuity, and address coupling and resonance issues. It requires constant efforts in technology, characterization and modeling in the field of flip-chip, micro-BGA, and also innovative approaches in embedded IC technology for RF and opto-RF packaging.
    Multiband applications are also becoming extremely important within passive development to realize multiple frequency bands for various wireless and optical subcarrier multiplexing (OSCM) systems. Advanced passives design for millimeter wave, smart antenna, and multibeam antenna require great attention as a next step in the realization of completely integrated wireless communication front-end systems.
    Quality factors and frequency limitation still limit RF front-end circuitry to large number of discrete passive components and make RF front-end module integration very critical. Furthermore, reconfigurable systems justify many works using MEMS technology to fabricate high-Q passives as well as RF MEMS switches on SOP modules. Design and fabrication have to be carried out to demonstrate that these devices can be directly included in a complete MEMS-SOP wireless integrated module.

ACKNOWLEDGMENT

    The authors would like to thank the National Science Foundation and the Georgia Electronic Design Center for their support. The authors would also like to thank the technical support of Drs. K. Lim and S. Pinel.

REFERENCES

Rao R. Tummala (Fellow, IEEE) received the Ph.D. degree in materials science and engineering from the University of Illinois, Urbana-Champaign, in 1968.     He is a Distinguished and an Endowed Chair Professor in Electrical and Computer Engineering and Materials Science and Engineering at the Georgia Institute of Technology (Georgia Tech), Atlanta. He is also the Founding Director of the National Science Foundation's (NSF) Engineering Research Center (ERC) in SOP technology called the Packaging Research Center (PRC). The PRC is the largest and most comprehensive microsystems packaging education and research center. He has published 270 technical papers and holds 68 U.S. patents and inventions.  Prof. Tummala is a Fellow of IMAPS and the American Ceramic Society, and a Member of the National Academy of Engineering and President of the IEEE-CPMT Society. He has received many awards including Industry Week's award as one of the 50 stars in the United States for improving U.S. competitiveness, the Third Millennium Award from IEEE, the Daniel Hughes and John Wagnon Award from IMAPS, the Materials Engineering Achievement Award from ASM International, the John Jeppson Award from the American Ceramic Society, the Total Excellence Award in Electronics Manufacturing (TEEM) Award from the Society of Manufacturing Engineers, and the European Materials Award (DVM). Most recently, he received the Distinguished Faculty Award from Georgia Tech. He is also an Eminent Scholar for the State of Georgia.

Joy Laskar (Senior Member, IEEE) received the B.S. degree in computer engineering from Clemson University, Clemson, SC, in 1985 and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign in 1989 and 1991, respectively.     He is the Joseph M. Pettit Professor of Electronics at the Georgia Institute of Technology (Georgia Tech), Atlanta. He is also the chair for the Electronic Design and Applications Technical Interest Group, the Director of Georgia's Electronic Design Center, and the System Research Leader for the NSF Packaging Research Center. He has authored or coauthored more than 200 papers, several book chapters (including three textbooks), and has ten patents pending. His research has focused on high-frequency IC design and their integration. At Georgia Tech, Dr. Laskar heads a research group with a focus on integration of high-frequency electronics with optoelectronics and integration of mixed technologies for next generation wireless and optoelectronic systems.     Dr. Laskar is the 1999 corecipient of the IEEE Rappaport Award, the recipient of the faculty adviser for the 2000 IEEE MTT IMS Best Student Paper Award, the 2001 Georgia Tech Faculty Graduate Student Mentor of the year award, the 2002 IBM Faculty Award, the 2003 Clemson's College of Engineering Outstanding Young Alumni Award, and the 2003 Outstanding Young Engineer of the Microwave Theory and Techniques Society Award.