Stability study of native epitaxial transistors as process probe for contamination detection

Methods for detecting contamination with native transistor probes are reviewed. This review is based on experience which was accumulated during development of multilevel epitaxial (EPI) high voltage DMOS process technologies including Deep Trench Isolation (DTI) with isolation capabilities up to and above 100V. Potential contamination sources, mechanisms and characterization are critically discussed. Authors identified five sources of dopant contamination: device EPI architecture, backside seal film budget, pre/post EPI cleans, cross tool contamination and high energy implants. Native NMOSFET device was used for detecting the low dopant contamination levels. Analyzing unique wafer patterns for native transistor threshold voltage can help point to a solution path.