Hybrid-cascaded modeling strategy for 28Gbps high-speed transceivers in high-density FPGA packages

In recent times, more customers are showing interest in high-speed serial link simulation as data rates are approaching 15–30Gbps. It is crucial for them to assess system performance since increasing data rates lowers system margin. Per pin package models accuracy considering package channel length variations and vias location is now critical as the effect in system performance variation can be relatively large. Hence, this paper proposes a highly efficient and accurate hybrid-cascaded modeling strategy to generate a substantial amount of per pin package high-speed transceiver S-parameter models for IBIS AMI model development and device link simulation. The proposed hybrid modeling technique splits the full package model structure into re-usable vertical via models with 3-D full-wave EM modeling and parameterized 2-D uniform horizontal trace modeling. The proposed methodology achieved good correlation with less than 7% discrepancy up to 70GHz model bandwidth. The accuracy is verified in both frequency and time domains comparing to the conventional full 3-D package channel modeling approach. Besides, package trace length grouping strategy is presented to maximize engineering efficiency improvement. Without impacting the system performance accuracy through system validation, similar trace length package channels are grouped and represented by a single package model. Overall, this modeling strategy is able to achieve 96% total lead time reduction comparing to the traditional modeling approach for a specific FPGA product family. Hence, the proposed modeling strategy provides great efficiency improvement without impacting system performance accuracy to provide quality per pin package transceiver S-parameter models for system link assessment. This is vital to ensure first design success rates for a FPGA solutions provider and its customers.