Reliability study of SiC-JFET including new copper, planar and silver based interconnection and joining technologies

The presented PC-results show that a direct transfer of conventional technologies like soldering and aluminum wire-bonding on SIC based module platforms might have minimal advantages if automotive requirements have to be satisfied. New die attachment technology like sintering shows a significant increase of life time expectation towards standard technologies (factor = 4). The configuration with sintered chips and copper wire bonds offers the best performance (factor = 20). Failure analysis provides two roote causes for module delamination: (1) Lift off between copper layer and SIC chip. (2) Degradation of the DBC-stack with focus on the copper cladding. If a further improvement of power cyling performance would be necessary, substrate reliability should be enhanced.