Performance comparison of 3 bit ECRL ADC with conventional logic style

Adiabatic circuits have been one of the preferred designs for reducing overall power dissipation in a circuit. By adiabatic technique, power dissipation in PMOS network can be reduced to optimal rates and some of energy stored at load capacitance can be recycled instead of losing it in the form of heat. Here in the given paper, the efficient charge recovery logic (ECRL) has been used to design one threshold inverter quantization (TIQ) based ADC. The design is then compared with a conventional CMOS ADC and parameters like power and delay has been checked. The entire circuit has been designed and simulated using CADENCE 180nm gpdk technology.