4Mbit DRAM design including 16-bit-concurrent ECC

An alpha-induced soft error becomes serious problem with increase in scale of dynamic RAM's(DRAM's). In order to achieve higher reliability for a high density digital memory system, not only the structure of an alpha immunity memory cell but also on-chip ECC(Error Checking and Correction) circuit should be considered. This paper describes an on-chip ECC circuit which checks 16 bit data concurrently. The ECC circuit is applied to 4Mbit DRAM.