Integration of III–V heterostructure tunnel FETs on Si using Template Assisted Selective Epitaxy (TASE)

Summary form only given. In this talk we will discuss fabrication and device aspects of IBMs work on III-V Tunnel FETs. Since our focus is on the monolithic integration of III-V on Si, we will show our recently developed Template Assisted Selective Epitaxy (TASE) technology and its application to both TFETs as well as other electronic devices. In TASE, III-V materials can be grown within templates, which allows for versatility in materials choice and freedom in growth parameters and is ideally suited for the heterojunction devices required for tunnel FETs. Generally, reducing traps at the heterojunction and at the interface is a great challenge for tunnel FETs, thus we will also discuss the impact of the different trap mechanisms in our devices.