A novel analytical capacitance model for sub-10 nm interconnects

Quick calculation of capacitance without field solver simulations is desirable to evaluate process assumptions and predict interconnect performance with minimal computation time. At sub-10 nm technology nodes complex interconnect stacks and shrinking dimensions preclude the use of empirical formulae. Here, we extend a physically based quick capacitance model to incorporate sub-10-nm technology elements such as damage layers, multilayer dielectric caps and non-rectangular interconnect cross-sections. The computation time of our model, implemented in standard spreadsheet software is negligible and validation with actual 10-nm node interconnect dimensions shows <1% error to field solver results. Our model also demonstrates good sensitivity to key process parameters. Our results would be useful to enable quick capacitance estimations for technology and process design.