Memory-aware and high-throughput hardware design for the HEVC fractional motion estimation

This paper presents a hardware design for the Fractional Motion Estimation (FME) of the High Efficiency Video Coding (HEVC) standard. The solution designed in this work uses a scheme to reduce the number of accesses to the reference frames stored in the external memory in up to 49.22%. A strategy to reduce the computational effort is also used. This strategy consists in using only the four square-shaped Prediction Unit (PU) sizes rather than using all the 24 possible PU sizes. This approach reduces the total encoding time in about 59%, with a bit-rate increase of only 4% for the same image quality. The hardware design was described in VHDL and synthesized for FPGA and ASIC technologies. The synthesis results for TSMC 65nm standard cells demonstrate that the developed design is able to process UHD 2160p videos at 60 frames per second (fps), reducing the required hardware resources in about five times when compared with the main related work.