A high-performance vertical substrate noise isolation method for 3D ICs

In this paper, we have developed a new structure to suppress 3D noise coupling in 3D silicon substrates. This technique consists of contact arrays and grid ground planes. The contact arrays suppress the low-frequency noise while the grid ground suppresses the high-frequency noise. This isolation method can be used for noise suppression between circuits and/or TSVs, and it can be applied in 3D ICs with multiple dies. This method is more efficient compared to guard rings. Results show that it has significant and stable performance.