Optimal modulation to reduce harmonics in inverters

Nowadays, there is a rapid development of devices of uninterruptible power supply (UPS) in communications. Inverter is one of the important parts in the UPS and its producing of current harmonics negatively affects the operation quality of communication devices. Therefore, reduction of current harmonics in the UPSs to achieve the stringent standards is one of the priority tasks of the inverters. Increasing the switching frequency of sinusoidal pulse-width modulation (SPWM) of inverters for reduction of current total harmonic distortion (THD) makes switching loss increase. This paper proposes an optimal SPWM technique, with variable switching cycle in every half of the fundamental period, for reducing the current harmonics, without any increase in switching loss. The results of the proposed technique are compared with those of the conventional constant switching cycle technique and the cascaded 5-level inverter to validate the performance of the proposed technique.