Heat transfer modelling of a dual-side cooled microprocessor chip stack with embedded micro-channels

The thermal management of 3D chip stacks is a limiting factor in dense system integration, due to the increased volumetric power density caused by multilayer thermal interfaces. Hence, novel cooling solutions will be a key driver in realisation of these 3D integrated chip stacks. In this work the performance of a dual-side water cooling system is analysed. A numerical method utilizing porous media approach is applied to extract design rules for the embedded channels within the chip stack.