Electrical interconnect test method of 3D ICs without boundary scan flip flops

An electrical interconnect test method and a testable design method are proposed of a 3D stacked ICs made of dies in which boundary scan flip flops are not embedded in this paper. Open defects occurring at interconnects between dies designed by the testable design method are detected by the test method. In order to examine feasibility of the electrical tests, a PCB circuit is tested by the test method made of a prototype IC designed by the testable design method. The experimental results show that a hard open defect and a resistive open one are able to be detected by the test method at a test speed of 500 kHz.