A physics-based compact model for Fully-Depleted Tunnel Field Effect Transistor

Tunnel FETs (TFET) are promising candidates for integration in logic circuits at very low supply voltages. We report here a SPICE compact model that describes all regimes of the TFET transistor. The current contribution from source and drain sides is described by an original set of equations including the electrostatic behavior and the effect of superlinear onset. Finally, this model is implemented using Verilog-A language and compared with TCAD simulations.