Low temperature charge pumping in SOI gated PIN diode

The recent progress of Si-based quantum electronics indicates the importance of silicon-on-insulator (SOI) materials, owing their unique characteristics, e.g., the ability to control the valley degree of freedom [1, 2]. Since such characteristics appear to be related to the quality of the Si/oxide interfaces, it is important to analyze the interface states in SOIs. However, the charge pumping (CP), the most reliable method for the interfacestate analysis [3-5], is not well established for the SOI devices, in particular at low temperatures. In this study, we perform systematic measurements of the CP current in an SOI gated PIN diode at 7 K. Mapping of the CP current in the front-gate/back-gate voltages plane reveals that the CP current is reduced when the dual (front and back) channels are formed. This anomaly is a unique feature of the low-temperature CP in SOI materials and indicates the importance of the interplay between the interface states and the remote channel.