Design of bit serial parallel multiplier using finite field over GF(2P)

Aggregation of finite field is the easiest of all finite field operations, but on the other side, in the field of arithmetic it is most frequently usable operations. On this Paper, we present simple but effective useful upgradation of the previous hardware design of finite field Aggregation over Galois Field, GF(2
^p
). Here we use Aggregation operation using p number of T flip flop instead of using combination of p number of XOR gate with equal number of D Flip flop Hooked loop structure so as to reduce critical path as well as Hardware complexity. The proposed finite field operations is used further for the implementation of bit serial parallel structure polynomial bases finite field multiplication and conversion of bit serial between polynomial bases representation and normal bases representation over GF(2
^p
). The area, time, delay, Hardware complexity is reduced in proposed Bit serial/Parallel multiplier is reduced of the proposed design.