MicroTCA at the Multiplexing Level in the readout of the PANDA micro vertex detector

The PANDA (AntiProton Annihilation at Darmstadt) detector system is under development for the future accelerator facility FAIR in Darmstadt, Germany. In the target spectrometer of PANDA a micro-vertex detector (MVD) will be used as the central tracking detector for charged particles. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the inner layers. Data from the readout ASICs in the front end are sent via GBT opical link (CERN development) to a Multiplexing Layer, where 3 GBT links are aggregated to 1 10 Gbit/s optical link to the Level-1 Trigger network. The Multiplexing Layer will be implemented with MTCA.4. The so-called HGF-AMC, a versatile AMC module developed by DESY in cooperation with KIT, will be used for the aggregation of the GBT links. The HGF-AMC is based on a Kintex-7 FPGA and supports MTCA.4.