Thermal stresses at interfaces in a semiconductor package

In conventional SiP (System in Package), several semiconductor chips had been 2D arranged in an interposer and a mother board. However, it is difficult to downsize and improve the performance of electronic devices due to that large area is occupied by the chips. Recently, 3D packaging technology has been investigated to reduce size of devices and to improve performance of semiconductor devices [1-11]. In particular, study on TSV (through silicon via) has been developed for stacked structure of semiconductor chips. TSVs are electrodes which are through semiconductor chip and conduct electrical signals between stacked semiconductor chips. TSV technology enables faster signal communication and downsizing of devices. 3D stacked structure developed by ASET (Association of Super-Advanced Electronics Technologies) and its enlarged structure are shown in Fig. 1 [10]. Many Cu-TSV are formed in three stacked semiconductor chips and SiO
2
-insulator and resin are formed as shown in its enlarged structure around TSV structure. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon and devices are broken by thermal stress which is depend on temperature increment. In case of reflow process, fracture of silicon and devices are also reported. In case of 3D-SIP, higher stresses are generated at interfaces and corner of electrical parts in globally and of materials in locally due to warp and mismatch of CTE (coefficient of thermal expansion) of materials. Therefore simulations which are focused on global area and local area are necessary for more accurate evaluation of fracture phenomena of 3D stacked package.