nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines

Low temperature (LT) activation on Fully Depleted Silicon On Insulator by SPER is needed for 3D sequential integration and also provides interest to obtain highly doped abrupt junctions in the standard planar technology. In this work, through the confrontation of electrical data and KMC process simulation we identify the efficient lever to optimize the low temperature device performance. This work evidences that the most suitable integration for LT FET implies a LDD implantation before the first spacer and the raised source drain epitaxy.