Segmented unbalanced super junction LDMOS for power integrated circuits

A high voltage SOI LDMOS with segmented unbalanced super junction (SJ) is proposed for the power integrated circuits. The concentration of p-pillar is higher than that of n-pillar at source SJ, but the concentration of n-pillar is higher at drain SJ. Segmented unbalanced SJ structure improves the lateral electric field distribution while it relieves the substrate-assisted depletion effects, which increases the breakdown voltage (BV) of lateral SJ device. Three-dimensional device simulation results indicate that a BV of 300 V is achieved for the proposed device with drift length of 15μm, compared with 130 V for conventional one and 245 V for the buffered SJ structure.