Novel TSV process technologies for 2.5D/3D packaging

"2.5D silicon interposers" and "Hetero 3D stacked" technology for high-performance LSI are gathering the most attention from now on. These technologies can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked each function devises. 2.5D and hetero-3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the long-term reliability of TSV production is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. “Scallop-free” etching process has developed for TSV fabrication [2]. As a result, the smooth-sidewall had proved shorten PVD process time [3]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electrochemical plating) in this paper. And then, a polyurea film using a vapor deposition polymerization technology (which is Ulvac's FPF/PV large panel technology) tried introduction as isolation liner for next-generation high frequency device. And, it performed the film formation to a TSV pattern.