Failure mechanism investigation of stacked via cracking in organic chip carrier

The increasing demand for high density interconnects leads to the adoption of stacked via technology. By layering multiple vias directly on top of each other, via stacking allows for more compact and flexible routing. However, due to the geometric discontinuity and non-uniform stiffness, stacked vias also present significant reliability challenges. In the investigation of via stack cracking mechanism in packaging applications, 16 types of stacked and staggered via chain structures were designed and fabricated in an organic chip carrier test vehicle. The experiments were also designed to evaluate other effects such as stacked via location, laminate materials, etc. Comparison of fail counts versus via chain types after 1000 cycles of deep thermal cycling (DTC) revealed that some types of stacked via structures are significantly more robust than others. Strong location dependency of stacked via fail was also observed by comparing the identical stacked via structure in different locations: out of 75 modules, 31 fails were detected in the stacked via chain under the chip center, but none under the chip corner. This paper focuses on the development of a predictive model with finite element method. Modeling activities were carried out to investigate the effect of via structure, package geometry, laminate material and other form factors on via cracking. The thermal-mechanical modeling methodology will be described in this paper. The discussion of failure mechanism and the correlation of simulations with experimental results will be presented.