Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology

For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3ppm/°C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.