Yield and reliability in 3D interconnect and WLP — Ultra thin chip stacking

This paper discusses the preconditions of thinned wafer with plasma back side stress relief (BSR) and chip side healing (CSH) processes applied in order to improve die strength allowing for stacking via pick and place preventing yield loss due to die cracking. As wafer thinning and singulating (dicing) leave scattered process marks (kerfs, chipping, micro cracks) on the chip, the thin die is prone to cracking when released from the wafer tape during a pick and place process.