Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope

A junctionless (JL) gate-all-around (GAA) nanosheet polycrystalline silicon (poly-Si) 2nm channel thin-film transistor (TFT) has been successfully demonstrated. The sub-threshold swing (SS) of 61 mV/decade has been the record reported to date in JL TFTs, and the I
_on
/I
_off
current ratio is 10
⁸
. The cumulative distribution in nanosheet 2-nm channel is small. JL-GAA TFTs show a low drain-induced barrier lowering (DIBL) value of 6 mV/V for L
_G
=60nm, excellent gate control and reduced sensitivity to temperature in terms of V
_TH
and SS. The JL-GAA TFTs of good device characteristics along with simple fabrication are highly promising for future (system-on-panel) SOP and system-on-chip (SOC) applications.