Sub-400 °C Si2H6 Passivation, HfO2 Gate Dielectric, and Single TaN Metal Gate: A Common Gate Stack Technology for In0.7Ga0.3As and Ge1-xSnx CMOS

We report a novel common gate-stack solution for In
_0.7
Ga
_0.3
As n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) and Ge
_0.97
Sn
_0.03
p-channel metaloxide-semiconductor field-effect transistors (pMOSFETs), featuring sub-400 °C Si
₂
H
₆
passivation, sub-1.75-nm capacitance equivalent thickness (CET), and single TaN metal gate. By incorporating Si
₂
H
₆
passivation, an ultrathin SiO
₂
/Si interfacial layer is formed between the high-k gate dielectric and the high mobility InGaAs and GeSn channels. The In
_0.7
Ga
_0.3
As nMOSFET and Ge
_0.97
Sn
_0.03
pMOSFET show drive currents of ~143 and ~69μA/μm, respectively, at |V
_DS
| and |V
_GS
- V
_TH
| of 1V for a gate length L
_G
of 4 μm. At an inversion carrier density N
_inv
of 10
¹³
cm
^-2
, In
_0.7
Ga
_0.3
As nMOSFETs and Ge
_0.97
Sn
_0.03
pMOSFETs show electron and hole mobilities of ~495 and ~230cm
²
/V·s, respectively. At N
_inv
of 4 × 10
¹²
cm
^-2
, electron and hole mobility values of ~705 and ~ 346cm
²
/V·s are achieved. Symmetric V
_TH
is realized by choosing a metal gate with midgap work function, and CET of less than 1.75nm is demonstrated with a gate-leakage current density (JG) of less than 10
^-4
A/cm
²
at a gate bias of V
_TH
± 1V. Using this gate-stack, a Ge
_0.95
Sn
_0.05
pMOSFET with the shortest L
_G
of 200nm is also realized. Drive current of ~680μA/μm is achieved at V
_DS
of -1.5V and V
_GS
- V
_TH
of -2V, with peak intrinsic transconductance G
_m,int
of ~492μS/μm at V
_DS
of -1.1V.