A 4Mb DRAM with double-buffer static-column architecture

A 4Mb CMOS DRAM organized 1Mb×4, measuring 6.35mm × 12.3mm, and operating at a typical row access time of 65ns, will be described. The design utilizes a double buffer architecture to achieve a static column access time of 25ns. Half V
dd
-folded bit-lines are used with a substrate plate trench storage structure resulting in a cell size of 10.5μm
²
.