An advanced submicron CMOS technology with 2 µm pitch at all levels

A CMOS technology with 2.0 µm pitch at isolation, poly, and metal interconnects is demonstrated using optical lithography. The "front-end" process defining the active regions uses a sealed interface process for bird's beak reduction and deep trenches in well-to-well isolation for latch-up suppression. The "back-end" process, where the metal interconnects are defined, replaces contacts and vias with posts. Metal posts (studs or pillars) were used to connect the first interconnect layer to poly and active regions and also to connect first and second interconnect layers. The resulting ring speed is 100 ps at 5.0 V for 0.8 µm (NMOS) and 0.9 µm (PMOS) channel lengths.