N- and p-well process compatibility in a 1 µm-CMOS technology

A 1 µm CMOS concept for 5 V supply-voltage with 22 nm gate oxide and a pure TaSi
2
gate is presented which allows to realize a n-well- and a p-well-process with widely compatible process flow. Starting in either case from 20 Ωcm epitaxial material on 0.02 Ωcm substrate the process uses equal well depths and identical low well dopant concentrations. Charge carrier mobilities have been found identical in both process concepts. N-channel low-level breakdown voltage is independent of the process concept used. Also independent of the well type the specific junction capacitances inside the well are nearly identical, outside the well typically different. Using ring oscillators with L
eff
=1.2 µm minimum propagation delays of 120ps for the p-well process and 190ps for the n-well process have been measured.