A low-voltage energy scalable static differential logic (ES2DL) family

A new logic family, Low-Voltage Energy Scalable Static Differential Logic (ES
²
DL), is proposed for portable digital signal processing (DSP) applications. ES
²
DL is capable of operating at supply voltages lower than the minimum of complementary CMOS logic. It achieves low-voltage operation while maintaining high speed of operation by reducing voltage swing and using body bias modulation. A 32-bit carry look-ahead adder (CLA), 8-bit carry-ripple adder (CRA), and a D-type flip-flop (DFF) have been designed and simulated. An ES
²
DL full-adder is shown to have an energy-delay product (EDP) saving of 2x to 6.5x compared to five other CMOS logic families.