A 65nm low power CMOS platform with 0.495/spl mu/m/sup 2/ SRAM for digital processing and mobile applications

In this paper, a 65nm CMOS platform featuring low power transistors and high density SRAM (CMOS5L) is reported. It offers wide range of Vth lineup and very low gate leakage as 0.06A/cm/sup 2/ by optimization of halo implantation and gate oxidation process. Pulse nitridation is applied to suppress Vth variations. Obtained characteristics of MOSFET places top class among devices reported. High density SRAM for CMOS5L with the cell size of 0.495/spl mu/m/sup 2/ is developed. We demonstrate highly stable operation by 7Mb CMOS5L SRAM array. This SRAM has low power property less than 100/spl mu/W.