Impact of oscillator power in discrete and continuous time /spl Sigma//spl Delta/ converters

This paper presents theory and simulations of clock oscillator jitter in continuous time and discrete time modulators with single bit feedback. The theory yields the output noise power of both discrete and continuous time modulators as a function of the power consumption of a ring oscillator producing the clock signal. Simulink simulations of 3rd order modulators have been included for comparison with the theoretical results, indicating that an oscillator power consumption 5 orders of magnitude higher in the continuous time case than in the discrete time case is needed, assuming a 98 dB signal to noise ratio is required.