Design of low power current-mode flash ADC

The design of a high-speed current-mode CMOS flash analog-to-digital converter (ADC) is presented. For high-speed operation, current mirroring technique with current comparison architecture is used and its advantages and limitations are explained. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance is investigated. A maximum sampling speed of 80 Ms/sec is achieved at 78 mW power consumption. The ADC is designed using 0.7-/spl mu/m CMOS technology.