Electrical design of wafer level package on board for gigabit data transmission

This paper discusses the design of a wafer level package on board for 5GHz data transmission. The design is based on the 2005 node of the International Technology Roadmap on Semiconductors (ITRS) that predicts a clock frequency of 5GHz, power of 170W and an operating voltage of 0.9V for high-end microprocessors. The goal of this paper is to demonstrate the ability to support global interconnections on the board at a speed comparable to the clock frequency and supply adequate power to the chip. This requires careful design of the topology of the interconnections, control of the eddy current losses in Silicon, control of the conductor and dielectric losses in the board and design of the transition between the chip and the board. The electrical design process is discussed in detail using a test vehicle, in this paper. The test vehicle consists of Co-planar waveguide (CPW) lines on high resistivity Silicon Substrate connected to CPW lines on low k, low loss board. The transition between the chip and board is completed through solder bumps with 50 /spl mu/m diameter and 100 /spl mu/m pitch. Both the Silicon and Board transmission lines have been characterized using TDR measurements. In addition, the inductance of the solder bumps have been extracted. Using synthesized models extracted from measurements, the eye diagrams for 5GHz data transmission has been simulated to show the importance of losses for 1mm long Silicon lines connected to 5cm long board lines through low inductance solder bumps. In addition, the effect of underfill and curing on signal propagation have been quantified.