A wide-margin, multiple-fan-in NOR gate for Josephson decoder

The design and testing of a Josephson-junction NOR gate with a fan-in of six used for a single-stage 6-bit decoder are reported. This NOR gate design has the advantages of very wide operating margins (about +or-67%, theoretically), insensitivity to global processing and/or temperature variations, and the capability of many fan-ins without trading off speed and margins. A cross section (3 bits) of a 6-bit decoder has been built and tested with +or-33% bias margin. The single NOR gate has been tested up to 2 GHz clock rate.<
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