Process design for merged complementary BiCMOS

A process sequence was designed to fabricate a fully complementary BiCMOS technology. In this technology, a merged bipolar-FET device structure and common subcollector p-n-p are used to implement a complementary emitter follower circuit, yielding a strong density advantage over conventional BiCMOS logic. The problems associated with the p-n-p subcollector formation, gate oxide protection, base formation, emitter protection and source/drain formation have been addressed. The result is a technology with a process complexity that is well-managed and has high performance.<
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