Implementation of high performance false contour reduction system using pattern analysis and error-predict method for PDP-HDTV

This paper proposes a high performance false contour reduction system with pattern analysis algorithm for PDP-HDTV. It also presents the optimized design and implementation of the method. The proposed method is verified using the Xilinx. Virtex-II FPGA XC2V2000-BG575. Furthermore, we suggest an advanced error-prediction algorithm for high performance. This method is demonstrated experimentally for a 50" PDP-HDTV.