Thermal limitations of InP HBT's in 80 and 160 Gbits/sup -1/ IC's

A 3D thermal model based on finite elements has been developed for the analysis of the thermal resistance of InP heterojunction bipolar transistors. The model was verified by comparing simulated and experimental results. The simulations also show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. By applying scaling laws, a road map for 80Gbit/s and 160Gbit/s devices is presented. Simulations show that devices suitable for 160Gbit/s circuits will be thermally possible if the InGaAs etch stop or contacting layer is removed from the sub collector.