Uniform internal model for hybrid language description

The HDL language, which is for hardware description, is not suitable for complex algorithmic programming, and while a high level language such as C describes algorithmic function effectively, it suffers when used for logic synthesis and verification. Development of system on a chip (SOC) leads to more and more components to be integrated into one chip. This paper represents a method which can deal with hardware components and algorithmic modules together through describing original units with C or VHDL and creating a uniform internal model, IIR (internal intermediate representation). The IIR internal model saves as an XML (Extensible Markup Language) format file externally. IIR can be used for partitioning, synthesis, and verification. By using the uniform model, analyzing source files repeatedly is avoided and the efficiency of research is improved.