Stress-induced voiding phenomena for an actual CMOS LSI interconnects

Stress induced voiding (SIV) phenomena in Cu damascene interconnect has been studied in detail considering the actual CMOS LSI design for the first time. In order to understand the SIV mechanisms, the test structures were designed to monitor the interconnect pattern dependency, the additional via effectiveness. The SIV in wide metal can be explained by considering effective diffusion area. Also, the SIV occurred in narrow metal line if it has wide metal reservoir, and this is explained. It has been also found that the SIV failure has been drastically reduced by lowering the via anneal temperature.