FinFET scaling to 10 nm gate length
Bin Yu; Leland Chang; Ahmed, S.; Haihong Wang; Bell, S.; Chih-Yuh Yang; Tabery, C.; Chau Ho; Qi Xiang; Tsu-Jae King; Bokor, J.; Chenming Hu; Ming-Ren Lin; Kyser, D.
Electron Devices Meeting, 2002. IEDM apos;02. Digest. International
Volume , Issue , 2002 Page(s): 251 - 254
Digital Object Identifier 10.1109/IEDM.2002.1175825
Summary: While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm. These MOSFETs are believed to be the smallest double-gate transistors ever fabricated. Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm). The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs. Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET. At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 1.2 V. Working CMOS FinFET inverters are also demonstrated.
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