A 16 mW 30 MSample/s 10 b pipelined A/D converter using a pseudo-differential architecture

The authors present a 16 mW 2 V 30 MSample/s 10 b pipelined A/D converter in 0.3 /spl mu/m CMOS technology which uses a pseudo-differential architecture and a capacitor cross-coupled S/H stage. SNDR and the SFDR at 30 MHz input are 54 dB and 67 dB, respectively.