Spacer FinFET: nano-scale CMOS technology for the terabit era

A spacer lithography process technology using a sacrificial layer and a CVD (Chemical Vapor Deposition) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are defined not by photolithography but by the CVD film thickness. Therefore the spacer lithography technology yields CD (Critical Dimension) variations of minimum-sized features which are much smaller than achieved by optical or e-beam lithography. It also provides a doubling of device density for a given lithography pitch. This spacer lithography technology is used to pattern Si-fin structures for double-gate MOSFETs (FinFETs), and CMOS FinFET results are reported.