A novel low jitter PLL clock generator with supply noise insensitive design

A novel control circuit is proposed to suppress the jitter caused by high frequency noise, which spectrum is beyond the loop bandwidth of the PLL used as clock generator in an USB2.0 application. Hspice simulates the circuits with BSIM3V3 model, and the cycle-to-cycle jitter is 1.68 ps when the VDD noise is 200 mv, 10 MHz square wave.