Fast locking clock generator using analog synchronous mirror delay technique with feedback control

With dual pumping ASMD as a core block, the proposed clock generator shows no phase quantization problem and also does not require replica of clock network. Also duty cycle correction is performed using selectable delay line with serial phase blend techniques. To verify the functionality of the proposed scheme, test chip is fabricated using 0.25 /spl mu/m 5 metal CMOS technology with 2.5 V supply. The measurement shows static phase error of <50 ps with frequency range of 250 MHz to 500 MHz having peak-to-peak jitter of 80 ps without external supply noise and that of 120 ps with /spl plusmn/500 mV 1 MHz rectangular noise at 333 MHz.