Design of a high performance PD SOI for the 0.18 /spl mu/m technology generation

This paper presents an optimized partially-depleted SOI device design for the 0.18 /spl mu/m CMOS technology generation and addresses several SOI unique floating-body effect issues which can affect the design. It is demonstrated that through proper device optimization, these undesired SOI-specific issues can be minimized to improve the manufacturability while maintaining high performance. Inverter delays of 5.1/4.7 ps at 1.5/1.8 V are achieved at low temperature. At room temperature, a delay of 12 ps is achieved at only 0.8 V supply voltage.