Implementation of a tunable heterodyne notch filter

Simple hardware implementations of three key elements, (1) a fixed-coefficient prototype filter. (2) the digital up-converter, and (3) a digital down-converter are proposed for realization in FPGAs or ASICs. Through layout and simulation the feasibility of a tunable heterodyne notch filter is established in which three up-converters, four notch filters and three down-converters are combined to build a complete tunable heterodyne notch filter with more flexibility and less complexity than conventional tunable notch filters.