Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5 nm and supply voltage of 1.5 V. The optimal performance is achieved by minimizing parasitic effects. The influence of experimental splits in source/drain (S/D) extension dose, S/D HDD dose and spike RTA on the reduction of series resistance and poly-depletion effect is studied. The role of the HALO implantation in optimization is investigated in detail.