Process integration of a direct-on-metal, non-etchback, /spl kappa/=2.5 spin-on polymer for the 0.18 /spl mu/m CMOS technology node

Process integration of a /spl kappa/=2.5 spin-on dielectric polymer into double-level metal CMOS parametric test structures at two technology nodes (0.35 /spl mu/m and 0.18 /spl mu/m) is described. This was accomplished using a single-coat, DOM (direct-on-metal), NEB (nonetchback) process. The structures are globally planarized using a standard CMP process on an oxide-based layer used to cap the low-k spin-on dielectric. Details of the process are presented together with electrical data demonstrating very low capacitance and low leakage current, even after multiple thermal cycles.