High frequency performance of a fully depleted 0.25-/spl mu/m SOI CMOS technology

A fully depleted (FD) 0.25-/spl mu/m silicon-on-insulator (SOI) CMOS process technology has been developed and established at Lincoln Laboratory. Here we describe the FDSOI process technology, report the high frequency performance of 0.25-/spl mu/m n- and p-channel MOSFETs and digital and analog circuits, and predict the performance of the FDSOI technology scaled to 0.1-/spl mu/m gate lengths.